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| #define SPI0_SCK_PA4_AF1 1 | ||
| #define SPI0_MOSI_PA3_AF1 1 | ||
| #define SPI0_MISO_PA2_AF1 1 | ||
| #define SPI0_MISO_PC3_AF3 1 | ||
| /* ======== SPI1 ======== */ | ||
| #define SPI1_SCK_PG6_AF1 1 | ||
| #define SPI1_MOSI_PG5_AF1 1 | ||
| #define SPI1_MISO_PG4_AF1 1 |
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| #define SPI0_SCK_PA4_AF1 1 | |
| #define SPI0_MOSI_PA3_AF1 1 | |
| #define SPI0_MISO_PA2_AF1 1 | |
| #define SPI0_MISO_PC3_AF3 1 | |
| /* ======== SPI1 ======== */ | |
| #define SPI1_SCK_PG6_AF1 1 | |
| #define SPI1_MOSI_PG5_AF1 1 | |
| #define SPI1_MISO_PG4_AF1 1 | |
| #define SPI0_SCK_PA4_AF1 | |
| #define SPI0_MOSI_PA3_AF1 | |
| #define SPI0_MISO_PA2_AF1 | |
| #define SPI0_MISO_PC3_AF3 | |
| /* ======== SPI1 ======== */ | |
| #define SPI1_SCK_PG6_AF1 | |
| #define SPI1_MOSI_PG5_AF1 | |
| #define SPI1_MISO_PG4_AF1 |
targets/arm/mikroe/common/include/mcu_definitions/TOSHIBA/TMPM4KLF10AFG/mcu_definitions.h
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| #define I2C0_SCL_PC1_AF4 1 | ||
| #define I2C0_SDA_PC0_AF4 1 | ||
| /* ======= I2C1 ======= */ | ||
| #define I2C1_SCL_PU1_AF3 1 | ||
| #define I2C1_SDA_PU0_AF3 1 |
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| #define I2C0_SCL_PC1_AF4 1 | |
| #define I2C0_SDA_PC0_AF4 1 | |
| /* ======= I2C1 ======= */ | |
| #define I2C1_SCL_PU1_AF3 1 | |
| #define I2C1_SDA_PU0_AF3 1 | |
| #define I2C0_SCL_PC1_AF4 | |
| #define I2C0_SDA_PC0_AF4 | |
| /* ======= I2C1 ======= */ | |
| #define I2C1_SCL_PU1_AF3 | |
| #define I2C1_SDA_PU0_AF3 |
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| /* ========================================== M4K(2) LQFP64 ========================================== */ | ||
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| /* ========================================== M4K(2) LQFP64 ========================================== */ | |
| /* ========================================== M4K(2) LQFP64 ========================================== */ | |
| @@ -0,0 +1,71 @@ | |||
| /**************************************************************************** | |||
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Remove file
| #endif | ||
| { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC } | ||
| }; | ||
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Remove double and triple empty lines and add an empty line at the end (all files!)
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| //EOF IVT_TABLE | ||
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| #endif // _MCU_DEFINITIONS_H_ | ||
| // ------------------------------------------------------------------------- END No newline at end of file |
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| // ------------------------------------------------------------------------- END | |
| // ------------------------------------------------------------------------- END | |
| @@ -0,0 +1,318 @@ | |||
| /**************************************************************************** | |||
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Review comments in this file can be applied to all mcu_definition.h files, so edit all of them accordingly.
esmaniksic
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Initial review
| @@ -0,0 +1,358 @@ | |||
| /**************************************************************************** | |||
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File name is missing the extension (.h)
targets/arm/mikroe/toshiba/include/gpio/hal_ll_gpio_constants.h
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| /*!< @brief UART pin structure. */ | ||
| typedef struct { | ||
| uint8_t module_index; | ||
| hal_ll_pin_name_t pin; | ||
| hal_ll_base_addr_t base; | ||
| uint8_t af; | ||
| } hal_ll_uart_pin_map_t; | ||
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| /*!< UART TX Pins. */ | ||
| static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { | ||
| // TODO - Define pin mappings here! | ||
| /*!< UART TX Pins. */ | ||
| static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { | ||
| #ifdef UART_MODULE_0 | ||
| #ifdef UART0_TX_PC0_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC0, HAL_LL_UART0_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #ifdef UART0_TX_PC1_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC1, HAL_LL_UART0_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART0_TX_PN1_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN1, HAL_LL_UART0_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART0_TX_PN0_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN0, HAL_LL_UART0_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #endif | ||
| #ifdef UART_MODULE_1 | ||
| #ifdef UART1_TX_PC5_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC5, HAL_LL_UART1_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART1_TX_PC4_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC4, HAL_LL_UART1_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #ifdef UART1_TX_PU6_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU6, HAL_LL_UART1_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART1_TX_PU5_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU5, HAL_LL_UART1_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #endif | ||
| #ifdef UART_MODULE_2 | ||
| #ifdef UART2_TX_PF1_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF1, HAL_LL_UART2_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART2_TX_PF0_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF0, HAL_LL_UART2_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #ifdef UART2_TX_PU1_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU1, HAL_LL_UART2_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART2_TX_PU0_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU0, HAL_LL_UART2_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #endif | ||
| #ifdef UART_MODULE_3 | ||
| #ifdef UART3_TX_PF4_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF4, HAL_LL_UART3_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART3_TX_PF3_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF3, HAL_LL_UART3_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #ifdef UART3_TX_PF7_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF7, HAL_LL_UART3_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART3_TX_PF6_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF6, HAL_LL_UART3_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #endif | ||
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| {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} | ||
| }; | ||
| {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} | ||
| }; | ||
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| /*!< UART RX Pins. */ | ||
| static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { | ||
| // TODO - Define pin mappings here! | ||
| /*!< UART RX Pins. */ | ||
| static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { | ||
| #ifdef UART_MODULE_0 | ||
| #ifdef UART0_RX_PC0_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC0, HAL_LL_UART0_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART0_RX_PC1_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC1, HAL_LL_UART0_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #ifdef UART0_RX_PN0_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN0, HAL_LL_UART0_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART0_RX_PN1_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN1, HAL_LL_UART0_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #endif | ||
| #ifdef UART_MODULE_1 | ||
| #ifdef UART1_RX_PC4_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC4, HAL_LL_UART1_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART1_RX_PC5_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC5, HAL_LL_UART1_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #ifdef UART1_RX_PU5_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU5, HAL_LL_UART1_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART1_RX_PU6_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU6, HAL_LL_UART1_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #endif | ||
| #ifdef UART_MODULE_2 | ||
| #ifdef UART2_RX_PF0_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF0, HAL_LL_UART2_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART2_RX_PF1_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF1, HAL_LL_UART2_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #ifdef UART2_RX_PU0_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU0, HAL_LL_UART2_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART2_RX_PU1_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU1, HAL_LL_UART2_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #endif | ||
| #ifdef UART_MODULE_3 | ||
| #ifdef UART3_RX_PF3_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF3, HAL_LL_UART3_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART3_RX_PF4_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF4, HAL_LL_UART3_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #ifdef UART3_RX_PF6_FR2 | ||
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF6, HAL_LL_UART3_BASE_ADDRESS, 2 }, | ||
| #endif | ||
| #ifdef UART3_RX_PF7_FR1 | ||
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF7, HAL_LL_UART3_BASE_ADDRESS, 1 }, | ||
| #endif | ||
| #endif | ||
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| {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} | ||
| }; | ||
| {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} | ||
| }; |
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| /*!< @brief UART pin structure. */ | |
| typedef struct { | |
| uint8_t module_index; | |
| hal_ll_pin_name_t pin; | |
| hal_ll_base_addr_t base; | |
| uint8_t af; | |
| } hal_ll_uart_pin_map_t; | |
| /*!< UART TX Pins. */ | |
| static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { | |
| // TODO - Define pin mappings here! | |
| /*!< UART TX Pins. */ | |
| static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { | |
| #ifdef UART_MODULE_0 | |
| #ifdef UART0_TX_PC0_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC0, HAL_LL_UART0_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART0_TX_PC1_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC1, HAL_LL_UART0_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART0_TX_PN1_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN1, HAL_LL_UART0_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART0_TX_PN0_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN0, HAL_LL_UART0_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_1 | |
| #ifdef UART1_TX_PC5_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC5, HAL_LL_UART1_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART1_TX_PC4_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC4, HAL_LL_UART1_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART1_TX_PU6_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU6, HAL_LL_UART1_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART1_TX_PU5_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU5, HAL_LL_UART1_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_2 | |
| #ifdef UART2_TX_PF1_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF1, HAL_LL_UART2_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART2_TX_PF0_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF0, HAL_LL_UART2_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART2_TX_PU1_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU1, HAL_LL_UART2_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART2_TX_PU0_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU0, HAL_LL_UART2_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_3 | |
| #ifdef UART3_TX_PF4_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF4, HAL_LL_UART3_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART3_TX_PF3_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF3, HAL_LL_UART3_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART3_TX_PF7_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF7, HAL_LL_UART3_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART3_TX_PF6_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF6, HAL_LL_UART3_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} | |
| }; | |
| {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} | |
| }; | |
| /*!< UART RX Pins. */ | |
| static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { | |
| // TODO - Define pin mappings here! | |
| /*!< UART RX Pins. */ | |
| static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { | |
| #ifdef UART_MODULE_0 | |
| #ifdef UART0_RX_PC0_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC0, HAL_LL_UART0_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART0_RX_PC1_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC1, HAL_LL_UART0_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART0_RX_PN0_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN0, HAL_LL_UART0_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART0_RX_PN1_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN1, HAL_LL_UART0_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_1 | |
| #ifdef UART1_RX_PC4_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC4, HAL_LL_UART1_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART1_RX_PC5_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC5, HAL_LL_UART1_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART1_RX_PU5_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU5, HAL_LL_UART1_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART1_RX_PU6_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU6, HAL_LL_UART1_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_2 | |
| #ifdef UART2_RX_PF0_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF0, HAL_LL_UART2_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART2_RX_PF1_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF1, HAL_LL_UART2_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART2_RX_PU0_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU0, HAL_LL_UART2_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART2_RX_PU1_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU1, HAL_LL_UART2_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_3 | |
| #ifdef UART3_RX_PF3_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF3, HAL_LL_UART3_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART3_RX_PF4_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF4, HAL_LL_UART3_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART3_RX_PF6_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF6, HAL_LL_UART3_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART3_RX_PF7_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF7, HAL_LL_UART3_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} | |
| }; | |
| {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} | |
| }; | |
| /*!< @brief UART pin structure. */ | |
| typedef struct { | |
| uint8_t module_index; | |
| hal_ll_pin_name_t pin; | |
| hal_ll_base_addr_t base; | |
| uint8_t af; | |
| } hal_ll_uart_pin_map_t; | |
| /*!< UART TX Pins. */ | |
| static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { | |
| #ifdef UART_MODULE_0 | |
| #ifdef UART0_TX_PC0_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC0, HAL_LL_UART0_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART0_TX_PC1_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC1, HAL_LL_UART0_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART0_TX_PN1_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN1, HAL_LL_UART0_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART0_TX_PN0_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN0, HAL_LL_UART0_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_1 | |
| #ifdef UART1_TX_PC5_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC5, HAL_LL_UART1_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART1_TX_PC4_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC4, HAL_LL_UART1_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART1_TX_PU6_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU6, HAL_LL_UART1_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART1_TX_PU5_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU5, HAL_LL_UART1_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_2 | |
| #ifdef UART2_TX_PF1_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF1, HAL_LL_UART2_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART2_TX_PF0_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF0, HAL_LL_UART2_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART2_TX_PU1_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU1, HAL_LL_UART2_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART2_TX_PU0_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU0, HAL_LL_UART2_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_3 | |
| #ifdef UART3_TX_PF4_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF4, HAL_LL_UART3_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART3_TX_PF3_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF3, HAL_LL_UART3_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART3_TX_PF7_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF7, HAL_LL_UART3_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART3_TX_PF6_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF6, HAL_LL_UART3_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} | |
| }; | |
| /*!< UART RX Pins. */ | |
| static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { | |
| #ifdef UART_MODULE_0 | |
| #ifdef UART0_RX_PC0_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC0, HAL_LL_UART0_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART0_RX_PC1_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC1, HAL_LL_UART0_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART0_RX_PN0_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN0, HAL_LL_UART0_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART0_RX_PN1_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN1, HAL_LL_UART0_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_1 | |
| #ifdef UART1_RX_PC4_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC4, HAL_LL_UART1_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART1_RX_PC5_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC5, HAL_LL_UART1_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART1_RX_PU5_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU5, HAL_LL_UART1_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART1_RX_PU6_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU6, HAL_LL_UART1_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_2 | |
| #ifdef UART2_RX_PF0_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF0, HAL_LL_UART2_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART2_RX_PF1_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF1, HAL_LL_UART2_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART2_RX_PU0_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU0, HAL_LL_UART2_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART2_RX_PU1_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU1, HAL_LL_UART2_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| #ifdef UART_MODULE_3 | |
| #ifdef UART3_RX_PF3_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF3, HAL_LL_UART3_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART3_RX_PF4_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF4, HAL_LL_UART3_BASE_ADDRESS, 1 }, | |
| #endif | |
| #ifdef UART3_RX_PF6_FR2 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF6, HAL_LL_UART3_BASE_ADDRESS, 2 }, | |
| #endif | |
| #ifdef UART3_RX_PF7_FR1 | |
| { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF7, HAL_LL_UART3_BASE_ADDRESS, 1 }, | |
| #endif | |
| #endif | |
| {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} | |
| }; |
| /* CGFSYSMENA bitovi za UART kanale (1 = supply, 0 = stop) */ | ||
| #define CGFSYSMENA_IPMENA_UART0_BIT 21 /* UART ch0, 1 po resetu */ | ||
| #define CGFSYSMENA_IPMENA_UART1_BIT 22 /* UART ch1, 0 po resetu */ | ||
| #define CGFSYSMENA_IPMENA_UART2_BIT 23 /* UART ch2, 0 po resetu */ | ||
| #define CGFSYSMENA_IPMENA_UART3_BIT 24 /* UART ch3, 0 po resetu */ |
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Co-authored-by: esmaniksic <[email protected]>
Co-authored-by: esmaniksic <[email protected]>
Co-authored-by: esmaniksic <[email protected]>
Co-authored-by: esmaniksic <[email protected]>
Co-authored-by: esmaniksic <[email protected]>
Co-authored-by: esmaniksic <[email protected]>
Co-authored-by: esmaniksic <[email protected]>
Co-authored-by: esmaniksic <[email protected]>
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